top of page
보라색 꽃

Our Products

It's a great opportunity to provide information about our products.

If you want to get more detail information or customer success story, please contact us.

old wood_edited.jpg

IO Planner

This is a machine learning based IO placement optimization tool. GUI based visualization of pad placement and IO ring has built up. As a result of initial IO placement, the size of design circuit is predicted.

AI-based Pad Placer

This AI-based pad placement engine is implemented reinforcement learning-based algorithm and layout functions for pad placement that meet the target chip area and design rules.


LDRC stands for Logical Design Rule Checker. This is a full customized tool and validates the library for violations of design rules specified as default inputs of Verilog netlist and liberty library.

Wafer Test Utility

This provides an environment for the analysis of wafer test results:

(1) integrated fail log, (2) time set list described in vector file, (3) modified vector file output.

Our Clients

GAONCHIPS-CI(Vertical Type)_edited_edite
별이 빛나는 밤
bottom of page