This is a machine learning based IO placement optimization tool. GUI based visualization of pad placement and IO ring has built up. As a result of initial IO placement, the size of design circuit is predicted.

This AI-based pad placement engine is implemented reinforcement learning-based algorithm and layout functions for pad placement that meet the target chip area and design rules.

LDRC stands for Logical Design Rule Checker. This is a full customized tool and validates the library for violations of design rules specified as default inputs of Verilog netlist and liberty library.

This provides an environment for the analysis of wafer test results:

(1) integrated fail log, (2) time set list described in vector file, (3) modified vector file output.