Developed electrical design automation software for the efficient PAD placement of system IC based on Artificial Intelligence algorithm.
Core Technology
“By adding a reinforcement learning-based pad placement function to the existing IO pad ring design tool, it is possible to optimize the pad placement that meets the target chip area.”
By applying PPO as a reinforcement learning algorithm, an environment that is easy to expand and change is built in consideration of future algorithm improvement and application of new algorithms.
Constructing a neural network that outputs batch action by inputting batch data as input, and developing an optimal action prediction function to determine chip presence through learning.
Developed LEF/DEF input/output parser for commercial P&R tools, a layout design tool, and APD I/O parser for the interface of a commercial package design tool.
Tool Performance
“Very fast pad placement speed with a satisfaction of the target chip area.”
As a result of the final development, the pad placement speed was reduced to less than 0.5 sec per piece, the chip area error rate of the pad placement result compared to the target chip area was lowered by 1.5%, and the interface implementation function of a commercial package design and P&R tools was confirmed.
Application Area
Applied to chip area prediction in the early design stage in system IC design, confirmation of pad placement possibility in the IO pad ring design stage, and prediction of optimal pad placement results in the silicon virtual prototyping or floor planning stage.